Error detection correcting circuit

Abstract

PURPOSE: To simplify a circuit and to sharply reduce the storage capacity of a memory by preparing check bits based upon 2n-bit data for a data processor capable of executing n-bit access and preparing only one error detection correcting circuit. CONSTITUTION: Each n-bit data are independently managed by an even/odd address and check bits consisting of m bits are formed and managed based upon the 2n-bit data consisting of both the even and odd addresses, and in either case of n-bit access and 2n-bit access, 2n bits are read out without fail. At the time of reading out n-bit data, only necessary n-bit read data are outputted to a CPU 31 after checking a 2n-bit error, and at the time of writing n-bit data, check bits are formed and stored based upon 2n bits consisting of the write data and the other n bits corresponding to the write data and necessary n bits are stored as write data. COPYRIGHT: (C)1992,JPO&Japio

Claims

Description

Topics

Download Full PDF Version (Non-Commercial Use)

Patent Citations (0)

    Publication numberPublication dateAssigneeTitle

NO-Patent Citations (0)

    Title

Cited By (0)

    Publication numberPublication dateAssigneeTitle